A first conventional memory apparatus includes a memory cell array for storing data, a data register composed of a plurality of latch circuits, a transfer gate connected between the memory cell array and the data register, and a selector which is a shift register and is connected to the data register.
In the first conventional memory apparatus, when an input serial data is supplied to the selector, the serial data is shifted by the number of bits, so that selection signals are supplied to corresponding latch circuits. The serial data is thereby latched. Then, the serial data is transferred to the memory cell array in parallel by the transfer gate, and is stored in the memory cell array. On the other hand, when the serial data is transferred to the data register in parallel by the transfer gate, the serial data is latched therein by the corresponding latch circuits. Then, the latched serial data is transferred to the shift register for the selector, in which the serial data is shifted to be supplied to a following state.
According to the first conventional memory apparatus, however, there is a disadvantage in that the structure is complicated because the shift register for the selector and the latch circuits for the data register require a number of elements to be used therein. Therefore, a cost of the memory apparatus is high.
A second conventional memory apparatus which overcomes the above disadvantage of the first conventional memory apparatus includes a memory cell array, a data register which is a shift register including a plurality of flip-flop circuits, and a transfer gate connected between the memory cell array and the data register.
The second conventional memory apparatus has been proposed in Japanese Patent Application No. 63-196708. In the second conventional memory device, when an input serial data is supplied to the data register bit by bit, the serial data is shifted therein in accordance with the clock signal. After that, when a last data bit of the serial data is stored in the data register, the serial data is transferred to the memory cell array in parallel by the transfer gate. On the other hand, when the stored data is transferred to the data register in parallel by the transfer gate, the transferred data is shifted therein to an output side of the register, so that the serial data is supplied to a following stage.
According to the second conventional memory device, however, there is a disadvantage in that, if the number of data bits composing a serial data is smaller than the total shifting steps, each being a flip-flop circuit of the shift register, invalid data bits of the number equal to the difference between those of the serial data bits and the shifting steps are supplied from the data register at the beginning time when the serial data is read out, as explained in detail later.